Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths

被引：33

作者：

Yoon, Jun-Sik ^{[1
,2
]}

Rim, Taiuk ^{[1
,2
]}

Kim, Jungsik ^{[3
]}

Meyyappan, Meyya ^{[3
,4
]}

Baek, Chang-Ki ^{[1
,2
,5
]}

Jeong, Yoon-Ha ^{[5
]}

机构：

[1] Pohang Univ Sci & Technol, Dept Creat IT Engn, Pohang 790784, South Korea

[2] Pohang Univ Sci & Technol, Future IT Innovat Lab, Pohang 790784, South Korea

[3] Pohang Univ Sci & Technol, Div IT Convergence Engn, Pohang 790784, South Korea

[4] NASA, Ames Res Ctr, Moffett Field, CA 94035 USA

[5] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 790784, South Korea

来源：

APPLIED PHYSICS LETTERS | 2014年 / 105卷 / 10期

关键词：

Nanowires;

D O I：

10.1063/1.4895030

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

Vertical gate-all-around (GAA) junctionless nanowire transistors (JNTs) with different diameters and underlap lengths are investigated using three-dimensional device simulations. The source-side diameter determines the on-current and drain-induced barrier lowering characteristics, whereas the drain-side diameter controls the band-to-band tunneling current during off-state conditions. The JNTs with short drain-side underlap lengths decrease the source/drain series resistance but increase the off-current values, especially due to large band-gap narrowing effects at the drain extension region. Proper device design of vertical GAA JNTs considering the device structure and underlap is needed to improve both on/off and short channel characteristics. (C) 2014 AIP Publishing LLC.

引用

页数：4

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Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]

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