Physical understanding of program injection and consumption in ultra-scaled SiN Split-Gate memories

被引：0

作者：

Masoero, L. ^{[1
]}

Molas, G. ^{[1
]}

Della Marca, V. ^{[2
]}

Gely, M. ^{[1
]}

Cueto, O. ^{[1
]}

Colonna, J. P. ^{[1
]}

De Luca, A. ^{[1
]}

Brianceau, P. ^{[1
]}

Charpin, C. ^{[1
]}

Lafond, D. ^{[1
]}

Delaye, V. ^{[1
]}

Aussenac, F. ^{[1
]}

Carabasse, C. ^{[1
]}

Pauliac, S. ^{[1
]}

Comboroure, C. ^{[1
]}

Boivin, P. ^{[2
]}

Ghibaudo, G. ^{[3
]}

Deleonibus, S. ^{[1
]}

De Salvo, B. ^{[1
]}

机构：

[1] CEA, LETI, MINATEC Campus,17 Rue Martyrs, F-38054 Grenoble 9, France

[2] STMicroelect, Rousset, France

[3] CNRS, IMEP LAHC, Grenoble, France

来源：

2012 4TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW) | 2012年

关键词：

CELLS;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this work, a detailed study of the physical mechanisms governing the Source Side Injection programming in ultra-scaled (down to 20nm) SiN split-gate memories is presented. Experimental measurements coupled to static and dynamic TCAD simulations are shown. In particular, we claim that adjusting the select gate voltage in moderate inversion allows for the optimization of the compromise between high electron injection and limited consumption. Then, we show that scaling the dimensions of the select gate can induce a higher consumption, while scaling the memory gate leads to lower programming energy (<1nJ) due to higher injection efficiency, suitable for low power applications.

引用

页数：4