Investigation of Chip-to-Chip Interconnections for Memory-Logic Communication on 3D Interposer Technology

被引：0

作者：

Neve, C. Roda ^{[1
]}

Ryckaert, J. ^{[1
]}

Van der Plas, G. ^{[1
]}

Detalle, M. ^{[1
]}

Beyne, E. ^{[1
]}

Pantano, N. ^{[2
]}

Verhelst, M. ^{[2
]}

机构：

[1] IMEC, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, MICAS ESAT, B-3001 Leuven, Belgium

来源：

2014 IEEE 18TH WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI) | 2014年

关键词：

silicon interposer; memory-logic communication; high-speed interconnections; test system emulators; Wide-IO;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A test system for memory-logic communications in silicon interposer is introduced as well as a performance analysis methodology including a fitted model based on eye diagram measurements. First results of the test system with 9 and 18 mm-long interconnects and a 5 channel bus of micro-strip lines with 2-2 and 5-5 mu m width and spacing (W-S), targeting Wide-IO communication standard are presented. Measured eye diagrams allow us to compare the performance of the different test systems in combination with a fitted model. All considered systems show operation frequencies higher than 200 MHz for an eye height of at least 35 %. It is demonstrated that the communication system performance is mainly dominated due to weak driver strength (R-S > 250 Omega) and secondly by the interconnection dimensions. Design considerations are proposed from the observed results.

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页数：4

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