Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives

被引:136
作者
Fong, Xuanyao [1 ]
Kim, Yusung [2 ]
Yogendra, Karthik [2 ]
Fan, Deliang [3 ]
Sengupta, Abhronil [2 ]
Raghunathan, Anand [2 ]
Roy, Kaushik [2 ]
机构
[1] ASTAR, Inst Microelect, Singapore 117685, Singapore
[2] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA
[3] Univ Cent Florida, Dept Elect Engn & Comp Sci, Orlando, FL 32816 USA
基金
美国国家科学基金会;
关键词
Boolean logic; magnetic tunnel junction (MTJ); neuromorphic computing; non-Boolean logic; nonvolatile memory; post-CMOS; spin-transfer torque (STT); spintronics; DOMAIN-WALL MOTION; MAGNETIC TUNNEL-JUNCTIONS; NONVOLATILE FLIP-FLOP; STT-MRAM; ENERGY-EFFICIENT; ORBIT TORQUES; ELECTRIC-CURRENT; PHASE-LOCKING; DRIVEN; MAGNETORESISTANCE;
D O I
10.1109/TCAD.2015.2481793
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As CMOS technology begins to face significant scaling challenges, considerable research efforts are being directed to investigate alternative device technologies that can serve as a replacement for CMOS. Spintronic devices, which utilize the spin of electrons as the state variable for computation, have recently emerged as one of the leading candidates for post-CMOS technology. Recent experiments have shown that a nano-magnet can be switched by a spin-polarized current and this has led to a number of novel device proposals over the past few years. In this paper, we provide a review of different mechanisms that manipulate the state of a nano-magnet using current-induced spin-transfer torque and demonstrate how such mechanisms have been engineered to develop device structures for energy-efficient on-chip memory and logic.
引用
收藏
页码:1 / 22
页数:22
相关论文
共 180 条
  • [31] A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory
    Chun, Ki Chul
    Zhao, Hui
    Harms, Jonathan D.
    Kim, Tae-Hyoung
    Wang, Jian-Ping
    Kim, Chris H.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (02) : 598 - 610
  • [32] A scalable neural chip with synaptic electronics using CMOS integrated memristors
    Cruz-Albrecht, Jose M.
    Derosier, Timothy
    Srinivasa, Narayan
    [J]. NANOTECHNOLOGY, 2013, 24 (38)
  • [33] Csaba G., 2012, Nanotechnology (IEEE-NANO), 2012 12th IEEE Conference on, P1, DOI DOI 10.1109/NANO.2012.6322201
  • [34] Computational Study of Spin-Torque Oscillator Interactions for Non-Boolean Computing Applications
    Csaba, Gyoergy
    Porod, Wolfgang
    [J]. IEEE TRANSACTIONS ON MAGNETICS, 2013, 49 (07) : 4447 - 4451
  • [35] Das Jayita, 2014, Proceedings of the 14th IEEE International Conference on Nanotechnology (IEEE-NANO), P859, DOI 10.1109/NANO.2014.6968027
  • [36] MRAM PUF: A Novel Geometry Based Magnetic PUF With Integrated CMOS
    Das, Jayita
    Scott, Kevin
    Rajaram, Srinath
    Burgett, Drew
    Bhanja, Sanjukta
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2015, 14 (03) : 436 - 443
  • [37] Voltage Asymmetry of Spin-Transfer Torques
    Datta, Deepanjan
    Behin-Aein, Behtash
    Datta, Supriyo
    Salahuddin, Sayeef
    [J]. IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2012, 11 (02) : 261 - 272
  • [38] Del Bel B., 2014, Proc. Design, P1
  • [39] Demidov VE, 2012, NAT MATER, V11, P1028, DOI [10.1038/NMAT3459, 10.1038/nmat3459]
  • [40] Driskill-Smith A., 2010, 2010 IEEE INT MEMORY, V1, P1