Design considerations in a BiCMOS dual-modulus prescaler

Design considerations in a dual modulus divide by 32/33 prescaler with a 0.6mum BiCMOS process are presented. Care was taken to design the ECL-based circuits to operate with as low supply voltage and current consumption as possible. The phase noise contribution of the integrated bandgap bias network is demonstrated through simulations. The trade-off between the power consumption and the phase noise is pointed out and some guidelines are provided to improve the noise performance, Measurements confirm the functionality of the prescaler with a 2.5 V supply drawing around 2.3 mA at 2.35 GHz with an input sensitivity between -24 dBm and 12 dBm. The circuit operates with a supply voltage down to 2.1 V but with limited input sensitivity.