Chaotic Encoder-Decoder on FPGA for Crypto System

被引：0

作者：

Roeksukrungrueang, Chanathip ^{[1
]}

Dittaphong, Xaysamone ^{[2
]}

Khongsomboon, Khamphong ^{[2
]}

Panyanouyong, Nounchan ^{[2
]}

Chivapreecha, Sorawat ^{[1
]}

机构：

[1] King Mongkuts Inst Technol Ladkrabang, Fac Engn, Dept Telecommun Engn, Bangkok 10520, Thailand

[2] Natl Univ Laos, Fac Engn, Dept Elect & Telecommun Engn, Laos PDR, Viangchan, Laos

来源：

2014 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) | 2014年

关键词：

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

An implementation of chaotic encoder-decoder on FPGA will be proposed in this paper. Overflow non-linearity by using 2's complement number in digital filter causes the phenomenon called "Chaos" in digital filter. An BR filter can be used to chaotic encoder while an FIR filter is used to chaotic decoder. Filter coefficients of both encoder and decoder can be compared to the secret key in private-key crypto system. However, if filter coefficients of chaotic decoder are not same as filter coefficients of chaotic encoder, ciphertext cannot decrypt to get original plaintext. Both chaotic encoder and decoder will be implemented on FPGA to demonstrate the hardware prototype of chaotic crypto system.

引用

页数：5

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