Design of New Multi-Column 5,5:4 Compressor Circuit Based on Double-Gate UTBSOI Transistors

In the modern electronic devices, compressor circuits are used to speed up the partial product addition (PPA) stage in the multipliers. This paper presents an architecture of multi-column 5,5:4 compressor whose new transistor level implementation has been carried out through the ultra-thin-body silicon-on-insulator (UTBSOI) transistors. Such compressor has been simulated in Cadence-spectre, and the performance parameters like power consumption and delay has been calculated at the rising and falling edge transition of input pulses. Advantage of the UTBSOI-compressor is further clarified from its comparison with the CMOS based design (CMOS-compressor). Simulation results reveal that the PDP exhibited by the UTBSOI-compressor is reduced by 79.89% than that of CMOS counterparts. Furthermore, to showcase the advantage of such compressor, it has been applied in the multiplier for PPA which offers approximate to 11.5% improvement in terms of power-delay-product (PDP) in the Virtex 6 platform. (C) 2019 The Authors. Published by Elsevier B.V.