Non-preemptible last section assignment for reducing feedback latency in real-time control systems

A real-time control system design procedure consists of the controller design stage and the implementation stage. In the controller design stage, various digital control theories are used with assumptions, such as synchronous sampling, no sampling jitter and negligible feedback latency (latency from sensing to actuation). However, in the implementation stage, multiple control tasks are usually scheduled on a processor, which creates a finite sampling period, varying feedback latency and sampling jitter, and therefore the controller's performance is degraded. In this article, we investigate the relationship between control performance and timing parameters. In the course of this investigation, we found that the feedback latency is the dominant factor affecting control performance. In addition, we propose a rate monotonic (RM) scheduler with non-preemptible last section algorithm, which can reduce the feedback latency considerably. The proposed algorithm provides better control performance than a preemptive RM scheduler, in most cases. The effectiveness of the proposed algorithm is shown in illustrative examples.