Common-Mode Voltage Regulation of Three-Phase SVPWM-Based three-Level NPC Inverter

被引：0

作者：

Umashankar, Subramaniam ^{[1
]}

Shankar, Vishnu Kalaiselvan Arun ^{[1
]}

Sanjeevikumar, Padmanaban ^{[2
]}

Harini, K. ^{[1
]}

机构：

[1] Vellore Inst Technol VIT Univ, Dept Energy & Power Elect, Vellore, Tamil Nadu, India

[2] Univ Johannesburg, Dept Elect & Elect Engn, Johannesburg, South Africa

来源：

ADVANCES IN POWER SYSTEMS AND ENERGY MANAGEMENT | 2018年 / 436卷

关键词：

Three-level neutral point clamped (NPC) inverters; Space vector modulation (SVM); Neutral point voltage balancing; MULTILEVEL INVERTERS; DESIGN; MODULATION; CONTROLLER;

D O I：

10.1007/978-981-10-4394-9_37

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the implementation of the modulation strategy to balance the neutral point potential (NPP) in three-level NPC inverters. This method employs the space vector pulse width modulation technique which gives the strong regulating ability of common-mode voltage of DC link capacitors. Apart from balancing the dc bus voltage this paper also examines the switching losses and junction temperature associated with the three-level inverters. The comparison of three-level inverter with two-level inverter, on the basis of switching losses, has also been explored. The performance of the modulation strategy to balance NPP has been validated and verified using MATLAB/Simulink.

引用

页数：10

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