Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects

A novel equalized global link architecture and driver-receiver codesign flow are proposed for high-speed and low-energy on-chip communication by utilizing a continuous-time linear equalizer (CTLE). The proposed global link is analyzed using a linear system method, and the formula of CTLE eye opening is derived to provide high-level design guidelines and insights. Compared with the separate driver-receiver design flow, over 50% energy reduction is observed. The final optimal solution achieves 20-Gb/s signaling over 10 mm, 2.6-mu m pitch on-chip transmission line with 15.5-ps/mm latency and 0.196-pJ/b energy using 45-nm technology. Monte Carlo simulation also shows that 3 sigma/mu for power and delay variation in the proposed global link are 13.1% and 4.6%, respectively.