Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects

被引：10

作者：

Weng, Shih-Hung ^{[1
]}

Zhang, Yulei ^{[2
]}

Buckwalter, James F. ^{[2
]}

Cheng, Chung-Kuan ^{[1
]}

机构：

[1] Univ Calif San Diego, Dept Comp Sci & Engn, La Jolla, CA 92037 USA

[2] Univ Calif San Diego, Dept Elect & Comp Engn, La Jolla, CA 92037 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2014年 / 22卷 / 04期

基金：

美国国家科学基金会;

关键词：

Continuous-time linear equalizer (CTLE); driver-receiver codesign; global link analysis; on-chip transmission-line; PERFORMANCE;

D O I：

10.1109/TVLSI.2013.2255070

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel equalized global link architecture and driver-receiver codesign flow are proposed for high-speed and low-energy on-chip communication by utilizing a continuous-time linear equalizer (CTLE). The proposed global link is analyzed using a linear system method, and the formula of CTLE eye opening is derived to provide high-level design guidelines and insights. Compared with the separate driver-receiver design flow, over 50% energy reduction is observed. The final optimal solution achieves 20-Gb/s signaling over 10 mm, 2.6-mu m pitch on-chip transmission line with 15.5-ps/mm latency and 0.196-pJ/b energy using 45-nm technology. Monte Carlo simulation also shows that 3 sigma/mu for power and delay variation in the proposed global link are 13.1% and 4.6%, respectively.

引用

页码：938 / 942

页数：5

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