S-parameter Models for transient simulation in Verilog-A

被引：0

作者：

Maier, Tobias ^{[1
]}

Droste, Dirk ^{[1
]}

Siegel, Michael ^{[2
]}

机构：

[1] Robert Bosch GmbH, Reutlingen, Germany

[2] IMS KIT, Karlsruhe, Germany

来源：

2013 9TH CONFERENCE ON PH. D. RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2013) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work presents a new method to model analog modules for transient simulations with their S-parameters and DC behavior. The model can be used for verification of analog circuits in a system simulation where the modeling is necessary to speed up transient simulations in analog domain for systems like Sigma Delta modulators (SDM) or DC/DC converters. The model includes circuitry to separate DC from AC in transient simulations to test various distortions on system level, like the power supply rejection. It is functional and shows high speed up for certain simulations.

引用

页码：249 / 252

页数：4

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