A 40MHz 70dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method

被引：0

作者：

Cortes, Fernando Paixao ^{[1
]}

Bampi, Sergio ^{[1
]}

机构：

[1] Univ Fed Rio Grande do Sul, PGMICRO Microelect Program, BR-91501970 Porto Alegre, RS, Brazil

来源：

SBCCI 2008: 21ST SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2008年

关键词：

Amplifier; CMOS analog design; RF front-end; Variable Gain Amplifier (VGA);

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper addresses the design of a 40MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70dB gain control range, using the g(m)/I-D design method. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 mu m CMOS process. The VGA dissipates 2.6mA from a 1.8V supply while occupying a 34,840 mu m(2) of chip area, excluding bond-pads.

引用

页码：76 / 80

页数：5

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