Architecture of a flexible on-board real-time SAR-processor

被引:0
|
作者
Langemeyer, S [1 ]
Simon-Klar, C [1 ]
Nolte, N [1 ]
Pirsch, P [1 ]
机构
[1] Leibniz Univ Hannover, Lab Informationstechnol, D-30167 Hannover, Germany
来源
IGARSS 2005: IEEE INTERNATIONAL GEOSCIENCE AND REMOTE SENSING SYMPOSIUM, VOLS 1-8, PROCEEDINGS | 2005年
关键词
D O I
暂无
中图分类号
P [天文学、地球科学];
学科分类号
07 ;
摘要
In compact airborne SAR systems on-board processing requires a programmable and compact Multi-DSP solution. At the Laboratorium fur Informationstechnologie (M), University of Hannover, a flexible Multi-DSP-Board has been developed. The architecture is based on the HiBRID-SoC, a programmable multi-core processor, optimized for SAR processing and image coding algorithms. Equiped with 6 HiBRID-SoOs a 233x175x15 mm board provides a realtime capability of processing SAR images with a raw data-rate of 50 MBit/s. Additional features are ROI support and image coding to reduce the required downlink bandwidth. The small volume and it's power consumption of less than 35 W enables it for on-board usage in air- or spaceborne systems. This paper presents the architecture of the system and explains how the different processing steps are mapped to the proposed hardware.
引用
收藏
页码:1746 / 1749
页数:4
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