SET logic driving capability and its enhancement in 3-D integrated SET-CMOS circuit

被引：11

作者：

Parekh, Rutu ^{[1
,2
]}

Beauvais, Jacques ^{[2
]}

Drouin, Dominique ^{[2
,3
]}

机构：

[1] Indian Inst Technol, Ctr Excellence Nanoelect, Bombay 400076, Maharashtra, India

[2] Univ Sherbrooke, Inst Interdisciplinaire Innovat Technol 3IT, Sherbrooke, PQ J1K 0A5, Canada

[3] Univ Sherbrooke, Lab Nanotechnol Nanosyst LN2, CNRS UMI 3463, Sherbrooke, PQ J1K 0A5, Canada

来源：

MICROELECTRONICS JOURNAL | 2014年 / 45卷 / 08期

关键词：

Drivability; Interface; Inverter; Interconnect parasitic; Hybrid SET-CMOS circuit simulation; SET-CMOS integration; Single electron transistor (SET); SINGLE-ELECTRON TRANSISTOR; DESIGN; SIMULATION;

D O I：

10.1016/j.mejo.2014.05.020

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The driving capability of a single-electron transistor (SET) circuit is sensitive to the load and interconnects. We discuss about improving the performance of a SET logic in hybrid SET-CMOS circuit by parameter variation and circuit architecture along with its simulation results. With an intention of studying the SET logic drivability in a SET-only circuit, we examined a circuit composed of 2(13) SET inverters with its interconnect effect in a 3-D CMOS IC. The schematic of the simulation is based on fabrication model of this large circuit along with interlayer and coupling capacitances of its metallization. The simulation results for delay, bandwidth and power validate the efficiency of a SET circuit. (C) 2014 Elsevier Ltd. All rights reserved.

引用

页码：1087 / 1092

页数：6

共 16 条

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