Low-power Carry Select Adder Using Fast All-one Finding Logic

A carry-select adder(CSA) can be implemented by using single ripple carry adder and an add-one circuit instead of using dual ripple-carry adders to reduce the area and power but with speed penalty. This paper proposes a new add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA, and no restrictions are imposed on the design of the adder blocks. For bit length n = 64, this new carry-select adders requires approximate 38 percent fewer transistors and 16 percent shorter delay than the original dual ripple-carry carry-select adder.