An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short-channel effects

被引:12
|
作者
Baral, Biswajit [1 ]
Das, Aloke Kumar [2 ]
De, Debashis [3 ]
Sarkar, Angsuman [4 ]
机构
[1] Silicon Inst Technol, ECE Dept, Bhubaneswar, India
[2] Abacus Inst Engn & Management, ECE Dept, Hooghly, India
[3] West Bengal Univ Technol, Dept CSE, Kolkata, India
[4] Kalyani Govt Engn Coll, ECE Dept, Kalyani, W Bengal, India
关键词
triple-material double-gate MOSFET; surface potential; drain-induced barrier lowering (DIBL); V-Th roll-off; subthreshold swing; TCAD simulation; DUAL-MATERIAL GATE; QUANTUM THRESHOLD VOLTAGE; SURFACE-POTENTIAL MODEL; ANALOG PERFORMANCE; DRAIN-CURRENT; SOI MOSFET; CMOS; INTEGRATION; SIMULATION; HALO;
D O I
10.1002/jnm.2044
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents an analytical subthreshold model for surface potential and threshold voltage of a triple-material double-gate (DG) metal-oxide-semiconductor field-effect transistor. The model is developed by using a rectangular Gaussian box in the channel depletion region with the required boundary conditions at the source and drain end. The model is used to study the effect of triple-material gate structure on the electrical performance of the device in terms of changes in potential and electric field. The device immunity against short-channel effects is evaluated by comparing the relative performance parameters such as drain-induced barrier lowering, threshold voltage roll-off, and subthreshold swing with its counterparts in the single-material DG and double-material DG metal-oxide-semiconductor field-effect transistors. The developed surface potential model not only provides device physics insight but is also computationally efficient because of its simple compact form that can be utilized to study and characterize the gate-engineered devices. Furthermore, the effects of quantum confinement are analyzed with the development of a quantum-mechanical correction term for threshold voltage. The results obtained from the model are in close agreement with the data extracted from numerical Technology Computer Aided Design device simulation. Copyright (c) 2015 John Wiley & Sons, Ltd.
引用
收藏
页码:47 / 62
页数:16
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