Comparison of TiSi2, CoSi2, and NiSi for thin-film silicon-on-insulator applications

被引:85
作者
Chen, J [1 ]
Colinge, JP [1 ]
Flandre, D [1 ]
Gillon, R [1 ]
Raskin, JP [1 ]
Vanhoenacker, D [1 ]
机构
[1] UNIV CATHOLIQUE LOUVAIN, MICROWAVE LAB, B-1348 LOUVAIN, BELGIUM
关键词
D O I
10.1149/1.1837833
中图分类号
O646 [电化学、电解、磁化学];
学科分类号
081704 ;
摘要
TiSi2, CoSi2, and NiSi self-aligned silicide processes have been studied, compared, and applied to thin-film silicon-on-insulator technology. Compared to TiSi2, CoSi2 and NiSi have the advantages of wider process temperature window, no significant doping retarded reaction, narrow runner degradation, and thin-film degradation. Therefore, they are more suitable for thin-film silicon-on-insulator technology. N-type field effect transistors have been fabricated in a complementary metal oxide-semiconductor compatible thin-film silicon-on-insulator technology with titanium, cobalt, and nickel self-aligned silicide processes for low-voltage, low-power microwave applications. The initial thicknesses of titanium, cobalt, and nickel are 30, 13, and 25 nm, respectively. The gate sheet resistances are 6.2, 4.4, and 2.9 Omega/square, respectively, and the total source/drain series resistances are 700, 290, and 550 Omega mu m, respectively. High-frequency measurement results are also presented.
引用
收藏
页码:2437 / 2442
页数:6
相关论文
共 20 条
[11]  
LAU CK, 1982, TECH DIG, P714
[12]  
MAEX K, 1995, PHYS WORLD NOV, P36
[13]  
MAEX K, 1995, SEMICOND INT, P75
[14]   SELF-ALIGNED NICKEL-MONO-SILICIDE TECHNOLOGY FOR HIGH-SPEED DEEP-SUBMICROMETER LOGIC CMOS ULSI [J].
MORIMOTO, T ;
OHGURO, T ;
MOMOSE, HS ;
IINUMA, T ;
KUNISHIMA, I ;
SUGURO, K ;
KATAKABE, I ;
NAKAJIMA, H ;
TSUCHIAKI, M ;
ONO, M ;
KATSUMATA, Y ;
IWAI, H .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (05) :915-922
[15]   ANALYSIS OF RESISTANCE BEHAVIOR IN TI-SALICIDED AND NI-SALICIDED POLYSILICON FILMS [J].
OHGURO, T ;
NAKAMURA, S ;
KOIKE, M ;
MORIMOTO, T ;
NISHIYAMA, A ;
USHIKU, Y ;
YOSHITOMI, T ;
ONO, M ;
SAITO, M ;
IWAI, H .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1994, 41 (12) :2305-2317
[16]  
Ostling M., 1995, PROPERTIES METAL SIL, P15
[17]   OPTIMIZATION OF SERIES RESISTANCE IN SUB-0.2 MU-M SOI MOSFETS (VOL 15, PG 145, 1994) [J].
SU, LT ;
SHERONY, MJ ;
HU, H ;
CHUNG, JE ;
ANTONIADIS, DA .
IEEE ELECTRON DEVICE LETTERS, 1994, 15 (09) :363-365
[18]   A SELF-ALIGNED COSI2 INTERCONNECTION AND CONTACT TECHNOLOGY FOR VLSI APPLICATIONS [J].
VANDENHOVE, L ;
WOLTERS, R ;
MAEX, K ;
DEKEERSMAECKER, RF ;
DECLERCK, GJ .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (03) :554-561
[19]  
WANG QF, 1995, S VLSI TECH, P17
[20]   SELF-ALIGNED SILICIDE TECHNOLOGY FOR ULTRA-THIN SIMOX MOSFETS [J].
YAMAGUCHI, Y ;
NISHIMURA, T ;
AKASAKA, Y ;
FUJIBAYASHI, K .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (05) :1179-1183