Void Formation Mechanism of Flip Chip in Package Using No-Flow Underfill

被引:9
作者
Lee, Sangil [1 ]
Yim, M. J. [1 ]
Baldwin, Daniel [1 ]
机构
[1] Georgia Inst Technol, George W Woodruff Sch Mech Engn, Atlanta, GA 30332 USA
关键词
differential scanning calorimetry; electronics packaging; flip-chip devices; lead; mass spectroscopic chemical analysis; solders; tin;
D O I
10.1115/1.3153369
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper investigates the void formation mechanism induced by chemical interaction between eutectic solder (Sn63/Pb37) wetting and no-flow underfill material curing during flip chip in package assembly. During the process, low weight molecular components, such as fluxing agents and water molecules, could be induced by the chemical interaction between solder wetting and underfill curing when these components are heated to melt and cure, respectively. The low weight molecular components become volatile with exposure to temperatures above their boiling points; this was found to be the main source of the extensively formed underfill voiding. This mechanism of chemically and thermally induced voids was explained using void formation study, differential scanning calorimetry thermogram comparison, and gas chromatography and mass spectroscopy chemical composition identification on the suggested chemical reaction formula. This finding can enhance understanding of the mechanism that drives no-flow underfill voiding and can develop a void-free flip chip assembly process using no-flow underfill material for cost effective and high performance electronics packaging applications. Furthermore, this study provides the design guideline to develop an advanced no-flow underfill having high performance at high temperature range for the lead-free application.
引用
收藏
页码:0310141 / 0310145
页数:5
相关论文
共 21 条
[1]  
CHEUNG AT, 2001, ELECT COMPONENTS TEC, V1315
[2]  
CHEUNG AT, 2000, ELECT MAT PACKAGING, V427
[3]  
COLELLA M, 2004, ADV PACKAGING MAT, V272
[4]  
COLELLA M, 2004, ELECT COMPONENTS TEC, V780
[5]  
Colella M., 2004, Mechanical Engineering
[6]   FLIP-CHIP ON BOARD CONNECTION TECHNOLOGY - PROCESS CHARACTERIZATION AND RELIABILITY [J].
GIESLER, J ;
OMALLEY, G ;
OMALLEY, G ;
WILLIAMS, M ;
MACHUGA, S .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1994, 17 (03) :256-263
[7]  
GOENKA L, 1996, IEEE CPMT INT ELECT, V430
[8]  
GOENKA L, 1995, IEEE CPMT INT ELECT, V14
[9]  
HURLEY JM, 2002, ELECT COMPONENTS TEC, V828
[10]  
LEE S, 2007, INT WAFER LEVEL PACK, V169