Verilog-A Compact Model for Oxide-based Resistive Random Access Memory(RRAM)

被引：0

作者：

Jiang, Zizhen ^{[1
,2
]}

Yu, Shimeng ^{[3
]}

Wu, Yi ^{[4
]}

Engel, Jesse H. ^{[1
,2
]}

Guan, Ximeng ^{[5
]}

Wong, H. -S. Philip ^{[1
,2
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

[2] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

[3] Arizona State Univ, Sch Comp Informat & Decis Syst Engn, Tempe, AZ 85281 USA

[4] Oracle Amer Inc, Belmont, CA USA

[5] IBM Res Corp, New York, NY USA

来源：

2014 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD) | 2014年

关键词：

RRAM; Compact model; variations; Verilog-A;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We demonstrate a dynamic Verilog-A RRAM compact model capable of simulating real-time DC cycling and pulsed operation device behavior, including random variability that is inherent to RRAM. This paper illustrates the physics and capabilities of the model. The model is verified using different sets of experimental data. The DC/Pulse parameter fitting methodology are illustrated.

引用

页码：41 / 44

页数：4

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