Enhanced Etch Process for TSV & Deep Silicon Etch

被引:0
|
作者
Xu, Qing [1 ]
Paterson, Alex [1 ]
McChesney, Jon [1 ]
Dover, Russell [1 ]
Yamaguchi, Yoko [1 ]
Eppler, Aaron [1 ]
机构
[1] Lam Res Corp, Fremont, CA USA
关键词
TSV; CIS; deep silicon etch; high etch rate; scallops;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
One of the key challenges of deep Si etch is feature control versus high etch rate. Scallop sizes increase with increased etch rate and uniformity degrades. This paper provides an overview of an enhanced rapid alternating process (RAP) in combination with a hardware design that breaks this trade off. Scallop control is achieved through very fast switching of gasses, bias and pressure (up to 10 times faster than the typical Bosch process). This new RAP is combined with a proprietary gas injection architecture to ensure uniformity of depth, both locally and across the wafer, by ensuring uniform dissociation of feedstock. Finally, this paper will show how a robust design has to address the challenges of increased thermal loads which can manifest as etch rate drifts and depth uniformity variations. The result is an increase in TSV throughput by > 200% and a reduction in scallop size by ten-fold.
引用
收藏
页码:426 / 428
页数:3
相关论文
共 50 条
  • [1] Wet Silicon Etch Process for TSV Reveal
    Mauer, Laura B.
    Taddei, John
    Youssef, Ramey
    Lu, Yongqiang
    Collins, Sian
    McLaughlin, Kevin
    Allen, Craig
    2014 IEEE 64TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2014, : 878 - 882
  • [2] Development and characterization of tapered silicon etch process by topography modeling for TSV application
    Ranganathan N.
    Malar A.
    Lee D.Y.
    Prasad K.
    Pey K.L.
    Journal of Microelectronics and Electronic Packaging, 2010, 7 (01): : 58 - 66
  • [3] Silicon Etch with Integrated Metrology for Through Silicon Via (TSV) Reveal
    Mauer, Laura B.
    Taddei, John
    Lawrence, Elena
    Youssef, Ramey
    Olson, Stephen P.
    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
  • [4] Effect of process parameters on sidewall damage in deep silicon etch
    Meng, Lingkuan
    Yan, Jiang
    JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2015, 25 (03)
  • [5] TSV Via Last Etch Integration Challenges and Etch optimization
    Loh, Woon Leng
    Ren, Qin
    Chui, King Jien
    2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC), 2015,
  • [6] Mask undercut in deep silicon etch
    Saraf, I.
    Goeckner, M.
    Goodlin, Brian
    Kirmse, Karen
    Overzet, L.
    APPLIED PHYSICS LETTERS, 2011, 98 (16)
  • [7] THE CONTROL METHOD OF SURFACE MORPHOLOGY AND ETCH RATES FOR SILICON ETCH PROCESS WITH EXTREMELY DEEP AND HIGH ASPECT RATIO
    Xu, Tiantong
    Tao, Zhi
    Tan, Xiao
    Li, Haiwang
    PROCEEDINGS OF THE ASME 5TH INTERNATIONAL CONFERENCE ON MICRO/NANOSCALE HEAT AND MASS TRANSFER, 2016, VOL 2, 2016,
  • [8] Influence of Bosch Etch Process on Electrical Isolation of TSV Structures
    Ranganathan, Nagarajan
    Lee, Da Yong
    Youhe, Liu
    Lo, Guo-Qiang
    Prasad, Krishnamachar
    Pey, Kin Leong
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (10): : 1497 - 1507
  • [9] A STUDY OF SILICON ETCH PROCESS IN MEMORY PROCESS
    Chang, Rong-Yao
    Zhang, Yi-Ying
    Zhang, Hai-Yang
    2017 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE (CSTIC 2017), 2017,
  • [10] Deep silicon etch for TSVs with improved via profile/process control
    Eaton, Brad
    Kumar, Ajay
    Pamarthy, Sharma
    SOLID STATE TECHNOLOGY, 2009, 52 (04) : 22 - +