A Novel Approach to Investigate the Impact of Hetero-High-K Gate Stack on SiGe Junctionless Gate-All-Around (JL-GAA) MOSFET

被引:15
作者
Gupta, Abhinav [1 ]
Rai, Sanjeev [2 ]
Kumar, Nitish [3 ]
Sigroha, Deepak [1 ]
Kishore, Arunabh [1 ]
Pathak, Varnika [1 ]
Rahman, Ziya Ur [1 ]
机构
[1] Rajkiya Engn Coll Sonbhadra, Dept Elect Engn, Churk 231206, India
[2] MNNIT Allahabad, Dept Elect & Commun Engn, Prayagraj 211004, India
[3] KIT, Dept Elect & Commun Engn, Kanpur 208001, Uttar Pradesh, India
关键词
JL-GAA MOSFETs; SCEs; DHGO; QHGO; THGO; Analog and RF FOMs; PERFORMANCE;
D O I
10.1007/s12633-020-00860-0
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
It is a well-known fact that the gate stacking is used to improve the electrostatic behavior of Si0.5Ge0.5 Junctionless Gate-All-Around (JL-GAA) MOSFETs. In gate stacking, the high-k oxide material is stacked with an interfacial silicon dioxide (SiO2) layer. In the recent past, oxide engineering techniques have been investigated as an alternative approach to improve the driving current of JL-GAA MOSFETs. In this paper, oxide engineering has been applied to improve the electrostatic performance of JL-GAA MOSFETs. The comparative study of the three device structures, namely Double Hetero gate oxide (DHGO), Triple Hetero gate oxide (THGO), and Quadruple Hetero gate oxide (QHGO) has been performed for various performance parameters. The objective behind this investigation is to highlight a significant enhancement in the driving current of JL-GAA MOSFETs. The comprehensive analysis shows that the DHGO device offers the highest ON-current, lowest subthreshold swing, and DIBL. Hence, the proposed device will be a perfect match for low power and high-speed communication systems.
引用
收藏
页码:1005 / 1012
页数:8
相关论文
共 21 条
[1]  
Abhinav Manish, 2017, 4 INT C SINGN PROC I, DOI [10.1109/SPIN.2017.8049955, DOI 10.1109/SPIN.2017.8049955]
[2]   Ultrathin body nanowire hetero-dielectric stacked asymmetric halo doped junctionless accumulation mode MOSFET for enhanced electrical characteristics and negative bias stability [J].
Baral, Kamalaksha ;
Singh, Prince Kumar ;
Kumar, Sanjay ;
Chander, Sweta ;
Jit, Satyabrata .
SUPERLATTICES AND MICROSTRUCTURES, 2020, 138
[3]   Electrical properties of SiO2/TiO2 high-k gate dielectric stack [J].
Bera, M. K. ;
Maiti, C. K. .
MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, 2006, 9 (06) :909-917
[4]   Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering [J].
Bousari, Nazanin Baghban ;
Anvarifard, Mohammad K. ;
Haji-Nasiri, Saeed .
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2019, 108 :226-234
[5]  
CHATTOPADHYAY A, 2020, SILICON NETH 0320, DOI DOI 10.1007/S12633-020-00430-4
[6]  
Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/NNANO.2010.15, 10.1038/nnano.2010.15]
[7]  
Dargar S.K., 2019, INT J ELECT ELECT EN, V8, P340, DOI [10.18178/ijeetc.8.6.340-345, DOI 10.18178/IJEETC.8.6.340-345]
[8]   A Full-Range Drain Current Model for Double-Gate Junctionless Transistors [J].
Duarte, Juan Pablo ;
Choi, Sung-Jin ;
Choi, Yang-Kyu .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (12) :4219-4225
[9]   Potential Modeling of Oxide Engineered Doping-Less Dual-Material-Double-Gate Si-Ge MOSFET and Its Application [J].
Gupta, Abhinav ;
Singh, Anamika ;
Gupta, S. K. ;
Rai, Sanjeev .
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2018, 13 (08) :1115-1122
[10]   Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region [J].
Holtij, Thomas ;
Schwarz, Mike ;
Kloes, Alexander ;
Iniguez, Benjamin .
SOLID-STATE ELECTRONICS, 2013, 90 :107-115