A 12.5 Gbps clock and data recovery circuit with phase interpolation based digital locked loop

This paper presents a high speed dual channel 12.5 Gbps receiver for serial link communication. Each channel consists of a continuous time linear equalizer (CTLE), a novel 12.5 Gbps dual loop clock and data recovery (CDR) circuit based on phase interpolation with only simple CML and CMOS logic, which makes the design simplicity and more tolerant to process, voltage and temperature variations. A single PLL shared by the two channel CDRs generates quadrature clock phases and distributes high frequency clock to each CDR for data recovery. The 12.5 Gbps two channel receiver prototype was designed in 65-nm CMOS technology with phase interpolation based digital locked loop, occupying an active area of 1.3 mm(2) and consuming a power of 300 mW from a 1.2 V power source.