Testing IP cores with pseudo exhaustive test sets

Testing core-based SOCs poses a big challenge to test engineers [1-4]. To test core-based SOCs, an important step is to get test sets for testing cores. Soft cores are usually provided with hardware description languages such as VHDL and Verilog. It is much more difficult to generate test sets at higher level than at logic level. Recent v, researchers have made efforts to develop test pattern generation algorithms and tools at RM level [5]. Function test is basically used for the test generation at high level [6]. Exhaustive function test can detect any,functional faults including multiple faults and the test pattern generation procedure is simple. However, exhaustive function test is unrealistic for practical application as too many test patterns are required. The alternative way is to use pseudo-exhaustive junction test, which can reduce the number of patterns while keep high fault coverage [7,8]. Pseudo-exhaustive tesing was first introduced by E.J. Macluskey, but it is limited to logic level (7]. In this paper, we propose a method to generate pseudo-exhaustive test sets at function level. The proposed method can be used to generate test sets for IP cores, specially, for soft sores.