Design Optimization for AC Coupled On-chip Global Interconnect

被引:0
|
作者
Liang, Lianfei [1 ]
Wang, Qin [1 ]
He, Weifeng [1 ]
Zeng, Xiaoyang [2 ]
机构
[1] Shanghai Jiao Tong Univ, Sch Elect Informat & Elect Engn, Shanghai 200240, Peoples R China
[2] Fudan Univ, Dept Microelect, Shanghai 200433, Peoples R China
来源
2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2016年
关键词
high speed; low power; interconnect; AC coupled; optimal design; COMMUNICATION;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
AC coupled low-swing signaling is a new method that can improve delay performance and reduce per-bit power consumption in communication. This paper first performs a delay analysis for AC coupled low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can dramatically increase the 3-dB bandwidth. Thus, the optimal design method can effectively improve the bandwidth of AC coupled global wires.
引用
收藏
页码:1521 / 1523
页数:3
相关论文
共 50 条
  • [31] A comparative analysis of a distributed on-chip RLC interconnect model under ramp excitation
    Coulibaly, LM
    Kadim, HJ
    EUROCON 2005: THE INTERNATIONAL CONFERENCE ON COMPUTER AS A TOOL, VOL 1 AND 2 , PROCEEDINGS, 2005, : 519 - 522
  • [32] A Closed-Form Analytical Transient Response Model for On-Chip Distortionless Interconnect
    Liu, Tony C.
    Kuo, James B.
    Zhang, Shengdong
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (12) : 3186 - 3192
  • [33] Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect
    Zhao, Wei
    Li, Xia
    Gu, Sam
    Kang, Seung H.
    Nowak, Matthew M.
    Cao, Yu
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2009, 56 (09) : 1862 - 1872
  • [34] Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis
    Patel, Nikita R.
    Agrawal, Yash
    Parekh, Rutu
    IETE JOURNAL OF RESEARCH, 2021, 67 (01) : 98 - 107
  • [35] Pulse Width Modulation for Reduced Peak Power Full-Swing On-Chip Interconnect
    Scott, Mackenzie
    Amirtharajah, Rajeevan
    ISLPED 09, 2009, : 213 - 218
  • [36] Optimal positions of twists in global on-chip differential interconnects
    Mensink, Eisse
    Schinkel, Daniel
    Klumperink, Eric A. M.
    van Tuijl, Ed
    Nauta, Bram
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (04) : 438 - 446
  • [37] Dynamics-dependent synchronization in on-chip coupled semiconductor lasers
    Ohara, Shoma
    Dal Bosco, Andreas Karsaklian
    Ugajin, Kazusa
    Uchida, Atsushi
    Harayama, Takahisa
    Inubushi, Masanobu
    PHYSICAL REVIEW E, 2017, 96 (03)
  • [38] Performace Modeling and Optimization for On-Chip Interconnects in Memory Arrays
    Mohseni, Javaneh
    Pan, Chenyun
    Naeemi, Azad
    2015 IEEE 24TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, 2015, : 149 - 151
  • [39] Driver pre-emphasis techniques for on-chip global buses
    Zhang, L
    Wilson, J
    Bashirullah, R
    Luo, L
    Xu, J
    Franzon, P
    ISLPED '05: PROCEEDINGS OF THE 2005 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2005, : 186 - 191
  • [40] Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA
    Gupta, Harshita
    Kabra, Mayank
    Patwari, Nitin D.
    Prashanth, H. C.
    Rao, Madhav
    2023 24TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, ISQED, 2023, : 24 - 32