Logic-based programming for wireless sensor-actuator networks

被引:3
作者
Wu, Yizhi [1 ]
Rowe, Anthony [1 ]
机构
[1] Carnegie Mellon Univ, Dept Elect & Comp Engn, Pittsburgh, PA 15217 USA
来源
2011 ACM/IEEE Second International Conference on Cyber-Physical Systems (ICCPS 2011) | 2011年
关键词
D O I
10.1109/ICCPS.2011.31
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper we present SAN-Logic, a lightweight logic-based programming paradigm that enables the dynamic progammability and configuration of sensor-actuator interactions in wireless sensor networks used to support Cyber-Physical Systems (CPS). Our goal is to simplify complex CPS design by providing a structured model of interactions that can be automatically mapped and deployed to a sensor-actuator network in an efficient and scalable manner. In contrast to sensor networking paradigms that distribute an application into individual sub-programs, SAN-Logic models the system as a set of boolean expressions which can be partitioned across the network like gates in a circuit. The user defines interactions as timed asynchronous sequential logic expressions [1] with sensors and actuators representing the inputs and outputs of the system. This approach is highly scalable since once deployed each interaction takes place as a sequence of independent and asynchronous events. This allows SAN-Logic to operate in a fully distributed manner without a central authority. Using this framework, optimization takes place across multiple tasks enabling sharing of resources within the network which will be an important part of future CPS. Redundant routes and the stateless nature of combinational logic (along with periodic state update messages) allow the system to easily cope with packet-loss and failed nodes. A major benefit of this approach is the ability to leverage existing hardware design and synthesis tools used by the VLSI design community. We demonstrate how boolean manipulation of the logic can be used to alter the mapping of expressions onto the network and hence can be used for optimization and verification. We provide an approach using logic simplification and mapping that reduces message passing by factoring common terms across different data paths within tasks and placing intermediate terms such that they benefit from shorter paths. In complex systems, we see on average a 40% reduction in message passing as compared to an implementation that does not optimize communication patterns within and across tasks.
引用
收藏
页码:163 / 173
页数:11
相关论文
共 21 条
[1]  
Ashar P., 1992, Sequential logic synthesis
[2]  
Brayton R.K., 1984, Logic minimization algorithms for VLSI synthesis
[3]  
Brayton R. K., 1987, IEEE COMPUTER AIDED
[4]  
Bryant R. E., 1986, Computers, IEEE Transactions on
[5]  
Cheong E., 2003, ACM S APPL COMP
[6]  
Cheong E., P C DES AUT TEST EUR
[7]  
ESWARAN A, 2005, IEEE REAL TIM SYST S
[8]  
Gummadi R., 2005, INT C DISTR COMP SEN
[9]  
Hnat T., 2008, ACM C EMB NETW SENS
[10]  
Hoque E., 2010, IEEE ACM C CYB PHYS