3D Stacked IC Demonstration using a Through Silicon Via First Approach

被引：0

作者：

Van Olmen, J. ^{[1
]}

Mercha, A. ^{[1
]}

Katti, G. ^{[2
]}

Huyghebaert, C. ^{[1
]}

Van Aelst, J. ^{[1
]}

Seppala, E. ^{[1
]}

Chao, Zhao ^{[1
]}

Armini, S. ^{[1
]}

Vaes, J. ^{[1
]}

Teixeira, R. Cotrin ^{[1
]}

Van Cauwenberghe, M. ^{[1
]}

Verdonck, P. ^{[1
]}

Verhemeldonck, K. ^{[1
]}

Jourdain, A. ^{[1
]}

Ruythooren, W. ^{[1
]}

de ten Broeck, M. de Potter ^{[1
]}

Opdebeeck, A. ^{[1
]}

Chiarella, T. ^{[1
]}

Parvais, B. ^{[1
]}

Debusschere, I. ^{[1
]}

Hoffmann, T. Y. ^{[1
]}

De Wachter, B. ^{[1
]}

Dehaene, W. ^{[2
]}

Stucchi, M. ^{[1
]}

Rakowski, M. ^{[1
]}

Soussan, Ph. ^{[1
]}

Cartuyvels, R. ^{[1
]}

Beyne, E. ^{[1
]}

Biesemans, S. ^{[1
]}

Swinnen, B. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, EE Dept, B-3001 Louvain, Belgium

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13 mu m CMOS process on 200mm wafers. The top die is thinned down to 25 mu m and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process.

引用

页码：603 / +

页数：2

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