A Circuit Design Method for Dynamic Reconfigurable Circuits

被引：0

作者：

Sawano, Hajime ^{[1
,2
]}

Kambe, Takashi ^{[3
,4
]}

机构：

[1] Kinki Univ, Grad Sch Sci & Engn, Higashiosaka, Osaka 577, Japan

[2] Kinki Univ, Sch Sci & Engn, Dept Elect & Elect Engn, Higashiosaka, Osaka 577, Japan

[3] Kinki Univ, Dept Elect & Elect Engn, Higashiosaka, Osaka 577, Japan

[4] Kinki Univ, Sch Sci & Engn, Higashiosaka, Osaka 577, Japan

来源：

ELECTRONICS AND COMMUNICATIONS IN JAPAN | 2014年 / 97卷 / 02期

关键词：

D O I：

10.1002/ecj.11577

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Reconfigurable computing (RC) is a new paradigm that addresses the conflicting design requirements of high performance and high area density. Coarse-grained architecture RC (CGA-RC) operates at the word level of granularity and exhibits better power and performance features than fine-grained architectures. However, in a CGA-RC system, the processing elements (PE) implement several types of arithmetic operations and the routing between them has a fixed architecture. To achieve both good performance and high PE utilization for all applications, this paper proposes an interactive circuit design methodology for dynamically reconfigurable processors to accelerate their performance and achieve compact circuits. The method is applied to a JPEG encoder design and its performance evaluated.

引用

页码：44 / 51

页数：8

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