A Circuit Design Method for Dynamic Reconfigurable Circuits

Reconfigurable computing (RC) is a new paradigm that addresses the conflicting design requirements of high performance and high area density. Coarse-grained architecture RC (CGA-RC) operates at the word level of granularity and exhibits better power and performance features than fine-grained architectures. However, in a CGA-RC system, the processing elements (PE) implement several types of arithmetic operations and the routing between them has a fixed architecture. To achieve both good performance and high PE utilization for all applications, this paper proposes an interactive circuit design methodology for dynamically reconfigurable processors to accelerate their performance and achieve compact circuits. The method is applied to a JPEG encoder design and its performance evaluated.