A 1-Gb/s, four-state, sliding block Viterbi decoder

To achieve unlimited concurrency and hence throughput in an area-efficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm, The SBVD approach reduces decode of a continuous input stream to decode of independent overlapping blocks, without constraining the encoding process, A systolic SBVD architecture-is presented that combines forward and backward processing of the block interval, The architecture is demonstrated in a four-state, R = 1/2, eight-level soft decision Viterbi decoder that has been designed and fabricated in double-metal CMOS, The 9.21 mm x 8.77 mm chip containing 150 k transistors is fully functional at a clock rate of 83 MHz and dissipates 3.0 W under typical operating conditions (V-DD = 5.0 V, T-A = 27 degrees C), This corresponds to a block decode rate of 83 MHz, equivalent to a decode rate of 1 Gb/s. For low-power operation, typical parts are fully functional at a clock rate of greater than 12 MHz, equivalent to a decode rate of 144 Mb/s, and dissipate 24 mW at V-DD = 1.5 V, demonstrating extremely low power consumption at such high rates.