Hardware Architecture for H.264/AVC INTRA 16X16 Frame Processing

被引：0

作者：

Loukil, H. ^{[1
]}

Arous, S. ^{[1
]}

Atitallah, A. Ben ^{[2
]}

Kadionik, P. ^{[3
]}

Masmoudi, N. ^{[1
]}

机构：

[1] Univ Sfax, Natl Sch Engn, BP W, Sfax 3038, Tunisia

[2] Univ Sfax, Inst High Elect & Commun, Sfax 3018, Tunisia

[3] Univ Bordeaux 1, CNRS, UMR 5218, IMS Lab ENSEIRB, F-33405 Talence, France

来源：

DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS | 2009年

关键词：

intra prediction; quantization; integer transform; Hardware Implementation; VHDL; H.264; ALGORITHM;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present an efficient H.264 / AVC Intra 16x16 Frame Coder System. The System achieves real-time performance for video conference applications. The INTRA 16X16 is composed by intra 16x16 prediction, integer transform, quantization AC, inverse integer transform, inverse quantization AC, quantization DC, hadamard, inverse quantization DC, and inverse integer transform. The proposed hardware is implemented in VHDL. The VHDL RTL code works at 160 MHz in an Altera Stratix II FPGA and it code 129 Mpixels per second. This work will be used as an Intellectual Property (IP) integrated in H.264/AVC encoder.

引用

页码：82 / +

页数：2

共 8 条

[1]

[Anonymous], H 264 MPEG 4 VIDEO C

[2] Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder [J].