Study of novel techniques for reducing self-heating effects in SOI power LDMOS

被引：31

作者：

Roig, J ^{[1
]}

Flores, D ^{[1
]}

Hidalgo, S ^{[1
]}

Vellvehi, M ^{[1
]}

Rebollo, J ^{[1
]}

Millán, J ^{[1
]}

机构：

[1] CNM CSIC, Ctr Nacl Microelect, Barcelona 08193, Spain

来源：

SOLID-STATE ELECTRONICS | 2002年 / 46卷 / 12期

关键词：

LDMOS; sol; SOIM; self-heating;

D O I：

10.1016/S0038-1101(02)00166-1

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented. (C) 2002 Elsevier Science Ltd. All rights reserved.

引用

页码：2123 / 2133

页数：11

共 26 条

[1] A 100-V LATERAL DMOS TRANSISTOR WITH A 0.3-MICROMETER CHANNEL IN A 1-MICROMETER SILICON-FILM-ON-INSULATOR-ON-SILICON [J].