Live Demonstration: FPGA-based CNN Accelerator with Filter-Wise-Optimized Bit Precision

To enhance the efficiency for inference of deep convolutional neural network without noticeable degradation of the recognition accuracy, we have proposed a filter-wise optimized quantization with variable bit precision. In addition, we have proposed the hardware architecture that fully supports the quantized variable bit precision. By using this hardware architecture, the execution time is reduced proportionally to the reduced bit precision by the filter-wise quantization. In the demonstration, we present image classification experiments on an FPGA where the proposed architecture is implemented with less execution time than the fixed 16-bit precision model.