Live Demonstration: FPGA-based CNN Accelerator with Filter-Wise-Optimized Bit Precision

被引：0

作者：

Nakata, Kengo ^{[1
]}

Maki, Asuka ^{[1
]}

Miyashita, Daisuke ^{[1
]}

Tachibana, Fumihiko ^{[1
]}

Suzuki, Tomoya ^{[1
]}

Deguchi, Jun ^{[1
]}

机构：

[1] Toshiba Memory Corp, Kawasaki, Kanagawa, Japan

来源：

2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2019年

关键词：

deep learning; convolutional neural network; quantization; variable bit width; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To enhance the efficiency for inference of deep convolutional neural network without noticeable degradation of the recognition accuracy, we have proposed a filter-wise optimized quantization with variable bit precision. In addition, we have proposed the hardware architecture that fully supports the quantized variable bit precision. By using this hardware architecture, the execution time is reduced proportionally to the reduced bit precision by the filter-wise quantization. In the demonstration, we present image classification experiments on an FPGA where the proposed architecture is implemented with less execution time than the fixed 16-bit precision model.

引用

页数：1

共 23 条

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