In every ASIC design project there comes a time that the design and its component parts must be functionally verified. In today's design environment, the design is usually described in an HDL and the majority of the verification task is accomplished using an HDL simulator. In preparation for the simulations, it is always required that at least some of the design hierarchy be successfully compiled. The first successful compile and the subsequent recompilations of a design expressed in VHDL is the focus of this paper. This paper details the use of GNU 'make' in controlling and automating the compile of VHDL designs. The paper focuses primarily on using 'make' in a hierarchical manner via a set of makefiles, in order to correctly compile the designs that utilize external, sharable, reusable and independently verified VHDL components. Secondarily the paper focuses on constructing the 'make' programs so that the compiles are done in the most efficient manner possible.
