Multi-column parallel QC-LDPC decoder architecture for NAND flash memory

被引：0

作者：

Shen, Wei ^{[1
]}

Chen, Cheng ^{[2
]}

Sha, Jin ^{[3
]}

机构：

[1] Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210046, Jiangsu, Peoples R China

[2] ZTE Corp, Microelect R&D Inst, Nanjing 210046, Jiangsu, Peoples R China

[3] Nanjing Univ, Shenzhen Res Inst, Nanjing 210046, Jiangsu, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2018年 / 15卷 / 10期

基金：

中国国家自然科学基金; 国家重点研发计划;

关键词：

QC-LDPC; NAND flash memory; column-based shuffle decoding; multiple-columns;

D O I：

10.1587/elex.15.20180397

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Quasi-cyclic (QC) low-density parity-check (LDPC) codes are famous for their excellent error correction performance and hardware friendly structure in NAND flash memory application. Array LDPC code is a type of highly structured QC-LDPC code that provides a good balance between performance and complexity. In this paper, a method is proposed for the construction of (18900, 17010) LDPC code that is based on the Latin square and an improved array dispersion strategy to achieve multi-column alignment of the structure. Compared with traditional design, the parallel hardware architecture reduces the number of barrel shifters by 32%. The corresponding ASIC implementation results show that the throughput of the proposed QC-LDPC code was up to 3.49 Gb/s and the throughput-to-area (TAR) of the proposed codes was significantly improved.

引用

页数：10

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