A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm tox, 1.8-V CMOS technology

被引：28

作者：

Sánchez, H ^{[1
]}

Siegel, J ^{[1
]}

Nicoletta, C ^{[1
]}

Nissen, JP ^{[1
]}

Alvarez, J ^{[1
]}

机构：

[1] Somerset Design Ctr, Austin, TX 78730 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 11期

关键词：

high-speed bus; I/O; level shifting; reliability; switch capacitor;

D O I：

10.1109/4.799854

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation.

引用

页码：1501 / 1511

页数：11