Simultaneous Switching Noise Analysis for High-Speed Interface

被引：0

作者：

Takahashi, Narimasa ^{[1
]}

Kagawa, Kenji ^{[2
]}

Honda, Yutaka ^{[2
]}

Takahashi, Yo ^{[3
]}

机构：

[1] IBM Japan Ltd, Kyoto 6048175, Japan

[2] ATE Serv, Kawasaki, Kanagawa 2130011, Japan

[3] Shibaura Inst Technol, Tokyo 1358548, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 04期

关键词：

SSN; power integrity; signal integrity; DDR;

D O I：

10.1587/transele.E92.C.460

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

引用

页码：460 / 467

页数：8

共 50 条

[31] Optimization analysis of high-speed differential signal vias in package
Luo, Jiahu
Yang, Huan
Qin, Wenjuan
Ma, XiaoJian
Liu, Weidong
2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2023,
[32] Analysis of Analog Power Rails in High-Speed Circuit Design
Erdin, Ihsan
2017 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY - EMC EUROPE, 2017,
[33] Investigation of a high-speed interconnect
Johansson, Christian
2020 IEEE 8TH ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2020,
[34] Power and Signal Integrity Analysis of High-speed Mixed-signal Backplane Based on VPX
Meng Hua
Niu Minxi
Tan Anju
Miao Jianghong
2018 IEEE SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SIGNAL INTEGRITY AND POWER INTEGRITY (EMC, SI & PI), 2018, : 577 - 581
[35] The Collaborative Design for the Package of High - speed Interface Chip
Bai, Lijuan
He, Huimin
Liu, Fengman
Li, Jun
Cao, Liqiang
2020 21ST INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2020,
[36] A systematic design to suppress wideband ground bounce noise in high-speed circuits by electromagnetic-bandgap-enhanced split powers
Wang, Chien-Lin
Shiue, Guang-Hwa
Guo, Wei-Da
Wu, Ruey-Beei
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2006, 54 (12) : 4209 - 4217
[37] Power Plane Noise Coupling To High Speed Signals
Demuynck, Filip
Eichinger, Ludwig
Poisson, Vincent
2015 IEEE 19TH WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI), 2015,
[38] Planar EBG Structure for Broadband Suppression of Simultaneous Switching Noise
Chen, Panpan
Wu, Qun
Shi, Shaorui
2016 IEEE INTERNATIONAL CONFERENCE ON ELECTRONIC INFORMATION AND COMMUNICATION TECHNOLOGY ICEICT 2016 PROCEEDINGS, 2016, : 578 - 582
[39] High dielectric constant thin film embedded capacitor for suppression of simultaneous switching noise and radiated emission
Kim, H
Park, H
Jeong, Y
Kim, J
Lee, S
Hong, J
Hong, Y
2004 INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, SYMPOSIUM RECORD 1-3, 2004, : 588 - 591
[40] Regression Algorithms Evaluation for Analysis of Crosstalk in High-Speed Digital System
Kim, Minhyuk
KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS, 2024, 18 (06): : 1449 - 1461

← 1 2 3 4 5 →