Simultaneous Switching Noise Analysis for High-Speed Interface

被引：0

作者：

Takahashi, Narimasa ^{[1
]}

Kagawa, Kenji ^{[2
]}

Honda, Yutaka ^{[2
]}

Takahashi, Yo ^{[3
]}

机构：

[1] IBM Japan Ltd, Kyoto 6048175, Japan

[2] ATE Serv, Kawasaki, Kanagawa 2130011, Japan

[3] Shibaura Inst Technol, Tokyo 1358548, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 04期

关键词：

SSN; power integrity; signal integrity; DDR;

D O I：

10.1587/transele.E92.C.460

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

引用

页码：460 / 467

页数：8

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