Study of wafer warpage for Fan-Out wafer level packaging: finite element modelling and experimental validation

被引:6
作者
Salahouelhadj, A. [1 ]
Gonzalez, M. [1 ]
Vanstreels, K. [1 ]
Podpod, A. [1 ]
Phommahaxay, A. [1 ]
Rebibis, K. [1 ]
Beyne, E. [1 ]
机构
[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium
来源
2019 20TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME) | 2019年
关键词
fan-out wafer level packaging; warpage; finite element analysis; stereo-digital image correlation; nanoindentation;
D O I
10.1109/eurosime.2019.8724578
中图分类号
O414.1 [热力学];
学科分类号
摘要
Wafer warpage is a big challenge during wafer process in Fan-Out Wafer-Level-Packaging (FOWLP). It is crucial to keep warpage low as much as possible for successful process integration. The warpage is mainly due to the Coefficient of Thermal Expansion (CTE) mismatch between the involved materials during temperature changes. Furthermore, warpage of molded wafers depends on material properties. Therefore, accurate material characterization has great importance. In this paper, thermal-mechanical properties of the used polymeric materials were measured using nanoindentation and Stereo-Digital Image Correlation (SDIC). In this study, warpage of molded wafers with and without Temporary Bonding Adhesive (TBA) is investigated during heating to 200 degrees C and cooling down to room temperature. SDIC technique was used to measure the warpage of molded wafers. Finally, Finite Element (FE) simulations were carried out using as input the measured thermal-mechanical properties. A comparison between warpage measurements and FE simulation at different temperatures showed a good agreement.
引用
收藏
页数:7
相关论文
共 14 条
[1]  
[Anonymous], CIRCUITS DEVICES MAR
[2]  
[Anonymous], 2009, IMAGE CORRELATION SH, DOI DOI 10.1007/978-0-387-78747-3
[3]  
Brinson HF, 2008, Polymer engineering science and viscoelasticity, DOI DOI 10.1007/978-1-4899-7485-3
[4]   Viscoelastic properties of polymer surfaces investigated by nanoscale dynamic mechanical analysis [J].
Chakravartula, A ;
Komvopoulos, K .
APPLIED PHYSICS LETTERS, 2006, 88 (13)
[5]   Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging [J].
Che, F. X. ;
Ho, David ;
Ding, Mian Zhi ;
MinWoo, Daniel Rhee .
2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2016, :1879-1885
[6]   Warpage Prediction and Experiments of Fan-Out Waferlevel Package During Encapsulation Process [J].
Deng, Shang-Shiuan ;
Hwang, Sheng-Jye ;
Lee, Huei-Huang .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (03) :452-458
[7]   Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging [J].
Lau, John H. ;
Li, Ming ;
Tian, Dewen ;
Fan, Nelson ;
Kuah, Eric ;
Kai, Wu ;
Li, Margie ;
Hao, J. ;
Cheung, Yiu Ming ;
Li, Zhang ;
Tan, Kim Hwee ;
Beica, Rozalia ;
Taylor, Thomas ;
Ko, Cheng-Ta ;
Yang, Henry ;
Chen, Yu-Hua ;
Lim, Sze Pei ;
Lee, Ning Cheng ;
Ran, Jiang ;
Xi, Cao ;
Wee, Koh Sau ;
Yong, Qingxiang .
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2017, 7 (10) :1729-1738
[8]   Embedded Wafer Level Ball Grid Array (eWLB) [J].
Meyer, T. ;
Ofner, G. ;
Bradl, S. ;
Brunnbauer, M. ;
Hagen, R. .
EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, :994-998
[9]   AN IMPROVED TECHNIQUE FOR DETERMINING HARDNESS AND ELASTIC-MODULUS USING LOAD AND DISPLACEMENT SENSING INDENTATION EXPERIMENTS [J].
OLIVER, WC ;
PHARR, GM .
JOURNAL OF MATERIALS RESEARCH, 1992, 7 (06) :1564-1583
[10]   A Novel Fan-Out Concept for Ultra-High Chip-to-Chip Interconnect Density with 20-μm Pitch [J].
Podpod, A. ;
Slabbekoorn, J. ;
Phommahaxay, A. ;
Duval, F. ;
Salahouedlhadj, A. ;
Gonzalez, M. ;
Rebibis, K. ;
Miller, R. A. ;
Beyer, G. ;
Beyne, E. .
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, :370-378