Design and VLSI architecture of non-polynomial based low probability of error (Pb) Viterbi decoder

This paper presents implementation of a new non-polynomial approach to design a high throughput with reduced bit error probability Viterbi decoder. Increase in d(free) has been achieved by proposed non-polynomial convolutional coding method. A decoder system (code rate k/n=1/6, constrain length K=4) has been implemented on Xilinx VERTEX-E. Performance of Viterbi decoder with proposed method has been improved from 27% to 75%. High speed (60.299 Mbps) and low bit error rate (BER) are achieved for Viterbi decoder. Proposed Viterbi decoder provides satisfactory probability of error (P-b) performance and high operating speed under conditions including AWGN, co-channel interference and adjacent channel interference environments.