Front-end CMOS chipset for 10 Gb/s communication

被引：28

作者：

Petersen, AK ^{[1
]}

Kiziloglu, KA ^{[1
]}

Yoon, T ^{[1
]}

Williams, F ^{[1
]}

Sandor, MR ^{[1
]}

机构：

[1] Intel Corp, Opt Components Div, Calabasas Design Ctr, Calabasas, CA 91302 USA

来源：

2002 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2002年

关键词：

D O I：

10.1109/RFIC.2002.1011931

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10 Gb/s communication chipset is realized for the first time in 0.18 mum generic CMOS. It comprises (all fully differential): (i) a transimpedance amplifier: gain=1300 Omega, bandwidth 9 GHz optical. (ii) a limiting amplifier: t(rise), r(fall) < 23 ps; sensitivity = 5 mV at BER = 10(-12). (iii) a laser driver: adjustable I-bias (up to 40 mA) and I-mod (up to 35 mA), driving a laser module with Z(in)=50 Omega.

引用

页码：93 / 96

页数：4

共 12 条

[1] Compact low-voltage power-efficient operational amplifier cells for VLSI [J].

de Langen, KJ ;

Huijsing, JH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (10) :1482-1496

[2] A fully integrated SiGe receiver IC for 10-Gb/s data rate [J].

Greshishchev, YM ;

Schvan, P ;

Showell, JL ;

Xu, ML ;

Ojha, JJ ;

Rogers, JE .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (12) :1949-1957

[3] A 0.6-W 10-Gb/s SONET/SDH fit-error-rate monitoring LSI [J].

Kawai, K ;

Ichino, H .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (12) :1988-1991

[4]

KIZILOGLU K, 2001, P NAT FIB OPT ENG C, P1237

[5]

LUNARDI L, 1997, P 1997 INT C IND PHO, P471

[6]

NAIR R, ISSC 2001, P224

[7]

OHTOMO Y, ISSCC 2000, P58

[8]

TANABE A, ISSCC 2001, P220

[9] 622 Mbit/s CMOS limiting amplifier with 40 dB dynamic range [J].

Yoon, T ;

Jalali, B .

ELECTRONICS LETTERS, 1996, 32 (20) :1920-1922

[10]

YOON T, 1998, S VLSI CIRC, P188

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