Semi-systolic architecture for AB2 operation over GF(2m)

This paper proposes a new algorithm and two parallel semi-systolic array architectures to compute AB(2) over GF(2(m)). They are based on the standard basis representation and use the property of irreducible all one polynomial as a modulus. The first architecture, named PSA(Parallel-in parallel-out Semi-systolic array Architecture) has the critical path with 1D(AND) + 1D(XOR) per cell and the latency of m+1. The second architecture, named MPSA(Modified Parallel-in parallel-out Semi-systolic array Architecture) has the critical path with 1D(XOR) per cell and has the same latency with PSA. They have lower latency and smaller hardware complexity than previous architectures. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation.