共 50 条
- [1] A Convolutional Code for On-chip Interconnect Crosstalk Reduction ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 145 - 148
- [2] Layout techniques for on-chip interconnect inductance reduction ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 269 - 273
- [3] Noise-aware power optimization for on-chip interconnect ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 108 - 113
- [4] Noise-aware power optimization for on-chip interconnect Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 2000, : 108 - 113
- [5] Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2003, : 93 - 96
- [6] A unified system level error model of crosstalk and electromigration for on-chip interconnect IEICE ELECTRONICS EXPRESS, 2017, 14 (05):
- [7] Testing for interconnect crosstalk defects using on-chip embedded processor cores 38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 317 - 320
- [8] Testing for interconnect crosstalk defects using on-chip embedded processor cores JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2002, 18 (4-5): : 529 - 538
- [9] Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores Journal of Electronic Testing, 2002, 18 : 529 - 538
- [10] A new analytical delay and noise model for on-chip RLC interconnect INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 823 - 826