Analytical models for crosstalk excitation and propagation in VLSI circuits

被引:26
作者
Chen, WY [1 ]
Gupta, SK [1 ]
Breuer, MA [1 ]
机构
[1] Univ So Calif, Dept Elect Engn, Los Angeles, CA 90089 USA
关键词
crosstalk; delay; noise; pulses; test generation;
D O I
10.1109/TCAD.2002.802276
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The authors develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high-speed circuits. They focus on crosstalk due to capacitive coupling between a pair of lines. Closed form equations are derived that quantify the severity of these effects and describe qualitatively the dependence of these effects on the values of circuit parameters, the rise/fall times of the input transitions, and the skew between the transitions. For noise propagation, they present a new way for predicting the output waveform produced by an inverter due to a nonsquare wave pulse at its input. To expedite the computation of the response of a logic gate to an input pulse, the authors have developed a novel way of modeling such gates by an equivalent inverter. The results of their analysis provide conditions that must be satisfied by a sequence of vectors used for validation of designs as well as postmanufacturing testing of,devices in the presence of significant crosstalk. They present data to demonstrate accuracy of their results, including example runs of a test generator that uses these results.
引用
收藏
页码:1117 / 1131
页数:15
相关论文
共 54 条
[1]  
[Anonymous], 1993, PRINCIPLE CMOS VLSI
[2]  
[Anonymous], P INT TEST C
[3]   Modeling and extraction of interconnect capacitances for multilayer VLSI circuits [J].
Arora, ND ;
Raol, KV ;
Schumann, R ;
Richardson, LM .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (01) :58-67
[4]  
Arunachalam R, 2001, DES AUT CON, P726, DOI 10.1109/DAC.2001.935601
[5]   TACO: Timing analysis with COupling [J].
Arunachalam, R ;
Rajagopal, K ;
Pileggi, LT .
37TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2000, 2000, :266-269
[6]  
ASTAVA RS, 1982, IEEE T ELECTRON DEV, V29, P1870
[7]   Process aggravated noise (PAN): New validation and test problems [J].
Breuer, MA ;
Gupta, SK .
INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS, 1996, :914-923
[8]   Fundamental CAD algorithms [J].
Breuer, MA ;
Sarrafzadeh, M ;
Somenzi, F .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (12) :1449-1475
[9]   PARAMETERIZED SPICE SUBCIRCUITS FOR MULTILEVEL INTERCONNECT MODELING AND SIMULATION [J].
CHANG, KJ ;
CHANG, NH ;
OH, SY ;
LEE, KY .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (11) :779-789
[10]   Analytic models for crosstalk delay and pulse analysis under non-ideal inputs [J].
Chen, WJ ;
Gupta, SK ;
Breuer, MA .
ITC - INTERNATIONAL TEST CONFERENCE 1997, PROCEEDINGS: INTEGRATING MILITARY AND COMMERCIAL COMMUNICATIONS FOR THE NEXT CENTURY, 1997, :809-818