An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI

被引：10

作者：

Vatanjou, Ali Asghar ^{[1
]}

Ytterdal, Trond ^{[1
]}

Aunet, Snorre ^{[1
]}

机构：

[1] Norwegian Univ Sci & Technol, Dept Elect Syst, N-7491 Trondheim, Norway

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 06期

关键词：

Level shifter; subthreshold; low-power; FDSOI; SUBTHRESHOLD; RANGE; CMOS;

D O I：

10.1109/TCSII.2018.2871637

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power level shifter capable of up-converting sub-50 mV input voltages to 1 V has been implemented in a 28 nm FDSOI technology. Diode connected transistors and a single-NWELL layout strategy have been used along with poly and back-gate biasing techniques to achieve an adequate balance between the drive strength of the pull-up and pull-down networks. Measurements showed that the lowest input voltage levels, which could be upconverted by the 10 chip samples, varied from 39 mV to 52 mV. Half of the samples could upconvert from 39 mV to 1 V. The simulated energy consumption of the level shifter was 5.2 fJ for an up-conversion from 0.2 V to 1 V and 1 MHz operating frequency.

引用

页码：899 / 903

页数：5

共 50 条

[11] Energy efficient low static-power voltage level shifter [J].

Maroof, Naeem ;

Sohail, Muhammad ;

Shin, Hyunchul .

IEICE ELECTRONICS EXPRESS, 2015, 12 (18)

[12] A Simple Ultra-Low Power Opamp in 22 nm FDSOI [J].

Kuzmicz, Wieslaw .

PROCEEDINGS OF THE 2019 26TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2019), 2019, :167-170

[13] FDSOI versus BULK CMOS at 28 nm node Which Technology for Ultra-Low Power Design? [J].

Makipaa, Jani ;

Billoint, Olivier .

2013 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2013, :554-557

[14] A Bluetooth Low Energy DCO in 28nm FDSOI [J].

Panetas-Felouris, Orfeas ;

Vlassis, Spyridon ;

Souliotis, George ;

Panagiotopoulos, Vasileios .

2020 43RD INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING (TSP), 2020, :321-324

[15] Design and Performance Parameters of an Ultra-Low Voltage, Single Supply 32bit Processor implemented in 28nm FDSOI Technology [J].

Clerc, S. ;

Abouzeid, F. ;

Patel, D. A. ;

Daveau, J-M. ;

Bottoni, C. ;

Ciampolini, L. ;

Giner, F. ;

Meyer, D. ;

Wilson, R. ;

Roche, P. ;

Naudet, S. ;

Virazel, A. ;

Bosio, A. ;

Girard, P. .

PROCEEDINGS OF THE SIXTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2015), 2015, :361-365

[16] Energy Efficient Memory Decoder Design for Ultra-Low Voltage Systems [J].

Viveka, K. R. ;

Amrutur, Bharadwaj .

2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014), 2014, :145-149

[17] A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI [J].

Tadros, Ramy N. ;

Hua, Weizhe ;

Moreira, Matheus T. ;

Calazans, Ney L. V. ;

Beerel, Peter A. .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (09) :858-862

[18] An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs [J].

Matsuzuka, Ryo ;

Hirose, Tetsuya ;

Shizuku, Yuzuru ;

Shinonaga, Kyohei ;

Kuroki, Nobutaka ;

Numa, Masahiro .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64 (08) :2026-2035

[19] A Tunable Ultra Low Power Inductorless Low Noise Amplifier Exploiting Body Biasing of 28 nm FDSOI Technology [J].

Zaini, Jennifer ;

Hameau, Frederic ;

Taris, Thierry ;

Morche, Dominique ;

Audebert, Patrick ;

Mercier, Eric .

2017 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2017,

[20] Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference [J].

Rezaei, Neda ;

Mirhassani, Mitra .

MICROELECTRONICS JOURNAL, 2021, 113

← 1 2 3 4 5 →