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- [22] Impact of trench sidewall interface trap in shallow trench isolation on junction leakage current characteristics for sub-0.25 mu m CMOS devices 1997 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1997, : 119 - 120
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- [25] LINEAR-FRESNEL-ZONE-PLATE-BASED 2-STATE ALIGNMENT METHOD FOR SUB-0.25 MU-M X-RAY-LITHOGRAPHY SYSTEM JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1993, 32 (12B): : 5977 - 5981
- [26] Sub-0.25 mu m ultra-thin SOI CMOS with a single N+ gate process for low-voltage and low-power applications 1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 80 - 81
- [27] Increase of parasitic resistance of shallow p+ extension with SiN sidewall process by hydrogen passivation of boron and its improvement by preamorphization for sub-0.25 mu m pMOSFETs 1996 SYMPOSIUM ON VLSI TECHNOLOGY: DIGEST OF TECHNICAL PAPERS, 1996, : 168 - 169
- [28] Reduced 1/f noise and g(m) degradation for sub-0.25 mu m MOSFETs with 25 angstrom-50 angstrom gate oxides grown on nitrogen implanted Si substrates 55TH ANNUAL DEVICE RESEARCH CONFERENCE, DIGEST - 1997, 1997, : 124 - 125
- [29] SUB-0.1 MU-M RESIST PATTERNING IN SOFT-X-RAY (13NM) PROJECTION LITHOGRAPHY JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1993, 32 (12B): : 5914 - 5917
- [30] 193 nm thin layer imaging performance of 140nm contact hole patterning and DOE dry development process optimization of multi-layer resist process ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XVII, PTS 1 AND 2, 2000, 3999 : 1028 - 1045