Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process

被引：69

作者：

Hazucha, P ^{[1
]}

Karnik, T ^{[1
]}

Walstra, S ^{[1
]}

Bloechel, BA ^{[1
]}

Tschanz, JW ^{[1
]}

Maiz, J ^{[1
]}

Soumyanath, K ^{[1
]}

Dermer, GE ^{[1
]}

Narendra, S ^{[1
]}

De, V ^{[1
]}

Borkar, S ^{[1
]}

机构：

[1] Intel Corp, Hillsboro, OR 97124 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 09期

关键词：

error control coding; radiation hardened latch; reliability; single event upset; soft error rate; soft errors;

D O I：

10.1109/JSSC.2004.831449

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V-T CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10 x better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.

引用

页码：1536 / 1543

页数：8

共 13 条

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