Two-dimensional threshold voltage model and design considerations for gate electrode work function engineered recessed channel nanoscale MOSFET: I

被引:3
作者
Chaujar, Rishu [1 ]
Kaur, Ravneet [1 ]
Saxena, Manoj [2 ]
Gupta, Mridula [1 ]
Gupta, R. S. [1 ]
机构
[1] Univ Delhi, Dept Elect Sci, Semicond Devices Res Lab, New Delhi 110021, India
[2] Univ Delhi, Dept Elect, Deen Dayal Upadhyaya Coll, New Delhi 110021, India
关键词
FIELD-EFFECT TRANSISTORS; EFFECT IMMUNITY; N-CHANNEL; DEGRADATION; RELIABILITY;
D O I
10.1088/0268-1242/24/6/065005
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper discusses a threshold voltage model for novel device structure: gate electrode work function engineered recessed channel (GEWE-RC) nanoscale MOSFET, which combines the advantages of both RC and GEWE structures. In part I, the model accurately predicts (a) surface potential, (b) threshold voltage and (c) sub-threshold slope for single material gate recessed channel (SMG-RC) and GEWE-RC structures. Part II focuses on the development of compact analytical drain current model taking into account the transition regimes from sub-threshold to saturation. Furthermore, the drain conductance evaluation has also been obtained, reflecting relevance of the proposed device for analogue design. The analysis takes into account the effect of gate length and groove depth in order to develop a compact model suitable for device design. The analytical results predicted by the model confirm well with the simulated results. Results in part I also provide valuable design insights in the performance of nanoscale GEWE-RC MOSFET with optimum threshold voltage and negative junction depth (NJD), and hence serves as a tool to optimize important device and technological parameters for 40 nm technology.
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页数:10
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