Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly

In sub-10 nm technology nodes, next generation lithography technologies are urgently required, and the diblock copolymer directed self-assembly (DSA) technology has shown its strong potential for contact/via layer fabrication. In addition, post-layout redundant via insertion has become a necessary step to guarantee sufficient yield and circuit reliability. However, existing redundant via insertion algorithms are not suitable for DSA since they could seriously deteriorate via manufacturability. In contrast, a sophisticated DSA-aware redundant via insertion algorithm may not only enhance circuit reliability but also improve DSA manufacturability. In this paper, we propose the first work of simultaneous guiding template optimization and redundant via insertion for DSA. An optimal integer linear programming (ILP)-based algorithm and an efficient graph-based approach are provided. To facilitate the development of the ILP formulation, a systematic approach is proposed to determine whether a via is manufacturable with DSA. In addition, reduction techniques are presented to greatly reduce the computational complexity of ILP. For the graph-based approach, all feasible via patterns composed of original vias and redundant vias are identified. Then, the original problem is transformed into a graph formulation and efficiently optimized. Experimental results show that both of our two algorithms can effectively optimize via manufacturability and maximize the redundant via insertion rate within reasonable computation time.